National Semiconductor promotes SP Devices' Interleaving Technology

Monday, 09 November 2009 10:00

SP Devices and National Semiconductor has previously announced collaboration regarding interleaving technology, both for 16 bit high resolution converters and 8-bit high speed converters. In this article Paul McCormack, Senior Applications Engineer at National Semiconductor Corp shows the benefits of SP Devices’ interleaving algorithm ADX combined with Giga Sample ADCs from National Semiconductor.

Link to article in EETimes

 
Product Information
Sample rate 140 - 1100 MSPS
Resolution 12 bit
Input signal range 0.25 or 2.2 Vpp1)
Input channels 1
Input bandwidth DC - 780 MHz 2)
Memory size 170 MSamples
Trigger Software/Ext./Level
Internal clock

Software selectable sample rate

External clock 0.25 - 2 Vpp
Interfaces USB 2.0 & PXIe
Dimensions 100 x 160 mm
Case dimensions 103 x 163 mm
1), 2) Depending on product options, see datasheet.

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  • ADQ214 - 2 Ch 14-Bit 400 MSPS

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