SP Devices

ADX is an interleaving post-correction digital IP with extreme performance. It removes distortions related to interleaving such as time-skew, offset- and gain- errors. Corrections are made transparently and in real time without any need of specific calibration signals. The IP is available in the delivery formats software IP, FPGA IP and silicon IP. For evaluation of the technology or examples of ADC array system design with the IP, SP Devices offers EVM hardware for different target specifications.

ADX Design Kit

The ADX Design Kits are the packages to use for in-design of the ADX IP on FPGAs. The kits contain all necessary contents to provide an easy integration.

2 ADC interleaving

ADX2 Design Kit Doubling the effective sampling rate Resolution up to 16 bits FPGA IP for Xilinx Virtex-5 devices

4 ADC interleaving

ADX4 Design Kit Quadrupling the effective sampling rate Resolution up to 16 bits FPGA IP for Xilinx Virtex-5 devices

Evaluation Modules

The ADX EVMs (EValuation Modules) are hardware platforms with specific ADC arrays interleaved in different configurations. Use the EVM to evaluate the ADX technology and ADX Design kit for implementing ADX into the target system. Combined with an ADX license, the EVM can also be used as a direct solution to a system's AD conversion. Customization of the EVMs for target systems is possible.

2.0 GSPS 12 bit

ADX4-EVM-2000/12 4 x 12-bit ADCs interleaved to 2000 MSPS In cooperation with

260 MSPS 16 bits

ADX2-EVM-260/16 2 x 16-bit ADCs interleaved to 260 MSPS In cooperation with

1.6 GSPS 14 bits

ADX4-EVM-1600/14 4 x 14-bit ADCs interleaved to 1600 MSPS In cooperation with

800 MSPS 14 bits

ADX2-EVM-800/14 2 x 14-bit ADCs interleaved to 800 MSPS In cooperation with

1.1 GSPS 12 bits

ADX2-EVM-1100/12 2 x 12-bit ADCs interleaved to 1100 MSPS

2.2 GSPS 12 bits

ADX4-EVM-2200/12 4 x 12-bit ADCs interleaved to 2200 MSPS In cooperation with

ADX Licenses

For the production of systems with the ADX interleaving IP, each individual system must be equipped with a run-time license. Licenses for FPGA IP is  supplied on a license EEPROM device (1-wire).

ADX2

Licenses for the ADX2 IP Delivered as license EEPROM for FPGA IP Contact SP Devices for volume pricing

ADX4

Licenses for the ADX4 IP Delivered as license EEPROM for FPGA IP Contact SP Devices for volume pricing

ADX Design services

SP Devices offer design services in both the analogue and digital domain to support system development with the ADX IP cores.

Design Support

ADX Design Services Support on analogue and digital integration of ADX Design services for board layouts Design services for customized signal processing