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Overview
The ADX2 Design Kit contains everything needed to integrate SP Devices proprietary ADX interleaving IP onto existing FPGA platforms. The IP continuously analyzes the ADCs' outputs to automatically remove the interleaving spurs arising from gain, offset and time skew mismatch errors, thereby removing the need for costly monitoring components and an off-line recalibration routine.
FPGA Platform Prerequisites
Intended target platforms must contain an ADC array of two (2) ADCs connected in parallel so that they share the same analog input signal. It must also be possible to clock the ADCs with inverted clocks.
Deliverables
The kit contains:
- User’s guide (including interface description, integration guidelines etc.)
- Software model (Windows DLL) of the ADX IP to be used for offline (non real-time) estimation/correction
- Xilinx ISE™ reference design project (example of integration)
- License-protected black-box Xilinx NGC for a specific FPGA device
- Verilog instantiation template for the black-box netlist
- Verilog simulation model (simple with correct latency) for behavioral simulation
- License-protected bitfile for the FPGA on the ADX-EVM (SX50T)
- Run-time limited development license for IP (on license EEPROM)
- Optional: ADX-EVM (Evaluation module HW) (with Xilinx SX50T) to use during development
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