ADX2-EVM-800/14

800 MSPS 14 bit

ADX2-EVM-800/14 2 x 14-bit ADCs interleaved to 800 MSPS In cooperation with

ADX EVM is a series of evaluation cards that demonstrate the power of SP Devices interleaving algorithms in various environment and applications. The ADX EVMs show how distortions related to interleaving such as time-skew, offset- and gain- errors are corrected. Corrections are made transparently and in real time without any need of calibration signals. The correction algorithm support a resolution of up to 16 bits, with a preserved SFDR of up to 95 dB, depending on the properties of the specific ADC array.

The ADX2-EVM-800/14 evaluation card is equipped with two, 14-bit, interleaved AD-converters demonstrating the capabilities of SP Devices IP block for interleaving of high-speed AD-converters. ADX EVM uses a Xilinx V5 series SX 50T FPGA for the signal processing of the interleaving algorithms and for storing of data batches used for evaluation of the algorithm. The card has a USB 1.1 port for communication with the FPGA and a on board memory of 64 kSample.

Setup and control of the evaluation card is made by the included software ADCaptureLab. The software contains useful analysis tools such as time series and FFT plots to facilitate the evaluation of the IP-block for the target application.

The ADX EVM is delivered with a time limited license and is intended for evaluation purposes only. The ADX EVM may also be delivered as part of an ADX Design Kit for FPGA IP as a platform for initial development.