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4 ADC
interleaving |
- ADX4 Design Kit
- Quadrupling the effective sampling rate
- Resolution up to 16 bits
- FPGA IP for Xilinx Virtex-5 devices
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ADX4 Design Kit |
The ADX4 Design Kit is the package to use for in-design of the ADX4 IP on FPGAs. The kit contains all necessary contents to provide an easy integration. The kit contains:
- Interface documentation
- License-protected black-box Xilinx NGC for a specific FPGA device (netlist).
- Run-time limited development license for IP (on license EEPROM)
- Verilog instantiation template for the black-box netlist.
- Verilog simulation model (simple with correct latency) for behavioral simulation
- Reference design ISE project (example of integration)
- License-protected bitfile for the FPGA on the ADX-EVM (SX50T)
- Optional: ADX-EVM (Evaluation module HW) (with Xilinx SX50T) to use during development
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