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Pulse Dynamic Range Extension (PDRX)

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Mass spectrometry performance is often determined by the achievable dynamic range of the underlying data acquisition system, and commercially available analog-to-digital converters (ADCs) often limit performance. A full bandwidth ADC with DC-coupled front-end operating at 2 Gigasample per second (GSPS) typically offers approximately 9 effective number of bits (ENOB). The Pulse Detection Range eXtension (PDRX) approach presented in this poster helps improve the dynamic range by an additional 3 bits. ​

A well-established approach is to acquire the input signal via two paths with different gain settings. The high gain channel is utilized to amplify and capture the low-amplitude portion of the input signal whereas the low gain channel is used to capture the full-scale input signal without causing saturation. Digital gain is then applied inside the onboard field-programmable gate array (FPGA) and the channels are combined to a single digital output with improved ENOB (figures 1 and 2). ​

  • FPGA pre-processing

Figure 1. PDRX Architecture​​​​​​.​​

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Figure 2. Channel re-combination.​

The signal split utilized in the dual-gain approach causes reflections and ringing. These unwanted artifacts are superimposed with the signal of interest and may partially distort or even completely “hide” the actual signal. By integrating the signal splitter inside the data acquisition board these negative effects can be minimized . It is also crucial to use analog-to-digital converters that can recover from over-range situations within less than one clock cycle. The digitized data is calibrated in the background to track the gain matching.

The increased dynamic range introduces new challenges as previously undetected signals are uncovered. One such example is signal reflections caused by impedance mismatch that may incorrectly be interpreted as ions (figure 3). This and other challenges are addressed with onboard real-time digital signal processing (DSP) for managing reflections at the digitizer (equalizer), reflections at the detector ( echo canceller ), pattern noise suppression, and baseline drift compensation for the AC-coupled detector. ​

  • Data reduction in the onboard FPGA is crucial

Figure 3. Previously undetected signal reflections are uncovered with improved dynamic range.​

  • Data reduction in the onboard FPGA is crucial

Figure 4. Temperature-dependant baseline drift can result in missed pulses if left uncorrected.​

Improving even further

Improving even further

Additional onboard real-time digital signal processing includes:

The use of the onboard FPGAs is crucial since it operates on the raw data stream and performs vital pre-processing and data reduction. They offer a high degree of parallelism, but computational resources such as multiply-accumulate (MAC) units are finite, and this can sometimes be limiting. One such example is Fast Fourier transform (FFT), where it can be challenging to implement long FFTs (with many frequency bins) inside the onboard FPGA.

These devices are typically programmed using hardware description languages (HDLs) such as VHDL or Verilog, although so-called high-level synthesis (HLS) can also be used. Without the onboard FPGAs, it would be impossible to adjust the raw data rate to fit the capacity of the data link to the host PC. In general, it is beneficial to perform as much pre-processing and data reduction as possible in the FPGA, but some processing is better done by post-processing in a GPU instead.

  • Digital baseline stabilizer (DBS) for a precise temperature-compensated baseline as a stable reference for determining peak height (figure 4).
  • Pulse detection firmware (FWPD) for data compression to list of peaks in the FPGA
  • Advanced time-domain firmware (FWATD) for noise suppression through thresholding and averaging of waveforms in the FPGA.

The data acquisition boards also support peer-to-peer (P2P) streaming to cost-efficient graphics processing units (GPUs) for post-processing. P2P offers a huge advantage compared to conventional solutions which require data to be copied via the RAM of the host PC. With P2P, both the CPU and RAM can instead be used for other tasks and data can be streamed at rates of 7 Gbyte/s.

GPU peer-to-peer streaming

By utilizing two 12-bit analog-to-digital converters we have achieved a dynamic range equivalent to commercial 16-bit converters. Currently available converters are limited to 1 GSPS sampling rate whereas our system supports 2.5 GSPS. We also intend to develop this further in order to reach 5 GSPS with maintained effective resolution and 2.5 GHz analog input bandwidth. This, therefore, corresponds to a five times higher sampling rate than what is available today ​
Resolution [bits] Cha​nnel Count​​​​ Sampling rate [GSPS] ​FPGA​ Interf​ace
ADQ32-PDRX​​ ​ 1 ​​12 ​1 2.5 Xilinx KU040

​PCIe​​​ ​​​​​
ADQ33-PDRX​​ ​ 1 ​​12 ​1 1 Xilinx KU040

​PCIe​​​ ​​​​​
ADQ35-PDRX​​ ​ 1 ​​12 ​1 5 Xilinx KU0115

​PCIe​​​ ​​​​​

1 PDRX utilize a d​ual-gain configuration in order to achieve a dynamic range equivalent to 12 ENOB. ​​​​​​​​​​​​

​LICPRDX​​​​​

Digitizers like ADQ3​2-PDRX offer onboard dual-gain signal splitter combined with digital signal processing (DSP) blocks such as digital gain, equalizer, and channel combination inside the FPGA. However, in some cases, customers want to utilize an external signal splitter as illustrated below.​

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With LICPDRX, customers gain access to the DSP blocks utilized in PDRX. This optional paid license enables PDRX as an add-on to existing firmware options (FWDAQ, FWPD, etc.) for selected dual-channel digitizers.

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The license can be purchased and installed retroactively on existing digitizers using the ADQLicenseUtil tool that is included free of charge in the software suite. Please refer to the digitizer datasheets to determine which specific models that support LICPDRX.

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