High-level synthesis (HLS) allows developers to create FPGA firmware using
commonly used high-level programming languages such as C or C++. Many
designers are more familiar with these languages than hardware description
languages (HDL) such as VHDL and Verilog, and the supported language
constructs help increase productivity. HLS allows the developer to focus
on high-level functionality rather than low-level details, and many
algorithms can be implemented more intuitively and efficiently using a
high-level programming language.
Teledyne SP Devices' firmware development kit is used together with Xilinx
Vivado® Design Suite that features built-in HLS support. We have recently
included an example for ADQ7 that demonstrates how to improve productivity
by generating (synthesizing) and verifying register transfer level (RTL)
implementations based on C++ source code. Please contact us if you would
like to know more.
New White Paper on Paritial Discharge
Partial discharges are electrical discharges occurring in the insulation
layer of electrical equipment (cables, switchgears, circuit breakers,
etc). They are called partial, as they do not completely bridge the space
between the two conducting terminals.
Partial discharge can occur in many parts of an electrical grid, where
high voltage exists and is surrounded by some type of insulation (solid,
liquid, air). Due to their localized and repetitive characteristics, they
build over time and result in insulation breakdown in transformers, power
cables, and cable accessories.
Learn more about how high-performance digitizers are used in partial
discharge monitoring for maintenance and preventive replacement planning
in power grids.
