When it comes to Swept-Source Optical Coherence Tomography, choosing the right digitizer is paramount. We offer a range of digitizers specifically designed to meet the rigorous demand of SS-OCT, ensuring high-performance data acquisition and precise measurement capabilities.

Key considerations when selecting a digitizer for SS-OCT applications 

• Direct Clocking vs. K-Clock Remapping: Directly using the k-clock for the digitizer has several drawbacks. A superior approach involves connecting the k-clock and OCT signal to analog inputs on the digitizer, digitizing both signals simultaneously while using a stable, high-precision clock source for optimal analog performance.
  • High-performance ADCs require low-jitter, high-quality clocks, which the k-clock cannot provide
  • The k-clock can exhibit noise or spikes and might be turned off during parts of the scan
  • ADCs prefer clocks with constant duty cycles, and varying cycles can lead to bad samples or data loss
  • Older-generation ADCs using parallel data interfaces limit sampling and A-scan rates
• K-Clock Remapping: The k-clock's varying frequency and k-clock remapping or resampling extract the desired SS-OCT samples, with interpolation estimating the OCT input amplitude at k-clock zero-crossings. This process, handled in real-time by the digitizer’s onboard FPGA, ensures accurate data capture.

Our FWOCT firmware introduces substantial enhancements in k-space remapping, refining signal processing workflows and outputs for SS-OCT devices. FWOCT's core functionality lies in the k-space remapping of OCT signals within the FPGA. FWOCT enables the use of advanced state-of-the-art analog-to-digital converters (ADCs) within digitizers.

Beneficially for Teledyne SP Devices' digitizers, spare open FPGA resources enable a master control system to be built able to manage the pulse data acquisition and characterization process as well as supplying pulsed laser control.

Why Teledyne SP Devices digitizers?

Teledyne SP Devices stands out in the field of SS-OCT digitizers for several reasons:

• Flexible digital k-space remapping in the onboard FPGA with multiple modes of operation:
  • Rising edge, rising and falling edge, higher degree of interpolation
  • Enables the use of lower k-clock/MZI clock frequencies
  • K-clock interpolation increases OCT sample points which increase image depth

• Crucial additional real-time signal processing blocks:
  • Background correction, windowing and dispersion compensation, FFT (8k, 32k), etc.

• Supports higher k-clock frequencies up to 2 GHz
• 14 Gbyte/s peer-to-peer streaming to GPU