FWOCT

Description

Our FWOCT firmware introduces substantial enhancements in k-space remapping, refining signal processing workflows and outputs for Swept-Source Optical Coherence Tomography (SS-OCT) devices. FWOCT's core functionality lies in the k-space remapping of OCT signals within the FPGA.

FWOCT enables the use of advanced analog-to-digital converters (ADCs) within digitizers. In SS-OCT applications, the k-clock establishes a non-uniform time base, while modern ADCs require a stable time base for consistent and reliable operation. To address this, FWOCT treats the k-clock and OCT signal as separate analog channels. By implementing sophisticated digital signal processing techniques, FWOCT optimizes ADC performance. This approach ensures that the ADC operates under optimal conditions, thereby improving signal quality. The fundamental principle of FWOCT is to translate the ADC's uniform time base to the k-clock's non-uniform time base in SS-OCT applications.

FWOCT supports three operational modes, providing significant flexibility in system architecture:

The k-clock/MZI can be adjusted across a wide range (4-2000 MHz for ADQ35).
The k-clock can operate at full rate or at a reduced frequency to lower cost and complexity.
OCT signal frequencies from 0 Hz up to 1 GHz (for ADQ32) and 2 GHz (for ADQ35) are supported.

Additional features include:

Data streaming to a GPU for further processing, with C-code examples available for AMD and Nvidia processors on both Windows and Linux platforms.
Streaming capabilities of 7 Gbyte/s for ADQ32 and 14 Gbyte/s for ADQ35.

FWOCT can be bypassed entirely, allowing all processing to be handled by the GPU. The ADQ3x series supports Open FPGA for custom code development.

Product	Resolution	Channels & Sampling rate [GSPS]	A-/B-scan trigger rate [MHz]	K-clock range [MHz]	OCT Signal Range [MHz]	FFT size (k)	Background Correction	Dispersion Compensation & Windowing	Output format (Absolute square or logarithmic.)	Streaming Rate to GPU/CPU (BG/s)
ADQ32	12	2 x 2.5	10	4 to 1000	0 to 1000	8	16-bit. 8k	16-bit. 8k	16-bit	7
ADQ33	12	2 x 1	10	1.6 to 400	0 to 400	8	16-bit. 8k	16-bit. 8k	16-bit	7
ADQ35	12	2 x 5	10	4 to 2000	0 to 2000	32	16-bit. 32k	16-bit. 32k	16-bit	14

Feature	Direct Clocking	K-space Remapping
Signal Connection	SS-OCT signal connected to digitizer analog input Ain1.	SS-OCT signal connected to digitizer input Ain1.
K-clock Connection	Limits maximum usable k-clock frequency (800MHz – 1 GHz).	Laser k-clock connected to digitizer input Ain2.
Clock Frequency Limitations	SS-OCT signal connected to digitizer analog input Ain1.	Enables use of higher k-clock frequencies.
Clock Source Stability	The Laser k-clock is not a stable clock source (some sources output very narrow glitches, others turn off during part of the scan).	The ADC is clocked normally with a precision fixed frequency clock source.
Compatibility	Works only with older generation ADCs.	Compatible with ADQ3x series, supports FWOCT (k-space re-mapping firmware).
ADC Design	ADCs are not designed to handle a variable clock frequency, leading to bad samples and data loss.	The interference signal is sampled in t-space using a constant clock, then re-sampled in the FPGA for linear k-space.
Data Integrity	Leads to bad samples and data loss.	Robust solution with no lost data or need to ignore the k-clock when k-space re-mapping is used.
K-space Re-mapping Requirement	K-space re-mapping in the FPGA is not necessary.	K-space re-mapping in the FPGA (FWOCT) is required.
Competitor Technology	Competitor ‘Ignore Bad Clock’ technology can ignore the k-clock signal for a user-specified time, leading to data loss during that period.	No equivalent workaround needed due to robust k-space re-mapping.
Data Capture	Ignoring the k-clock leads to lost data during that period.	The k-clock is continuously sampled, and every data point from the interference signal is captured.
K-clock Limitation	Limited by k-clock frequency variability.	K-clock is only limited by ADC sample rate (40%). ADQ32 supports 1GHz, ADQ35 supports 2 GHz k-clock.
Image Resolution and Capture Time	Limited by the clock frequency and stability.	Enables better image resolution and faster image capture time.
Image Resolution and Capture Time	Limited by the clock frequency and stability.	Enables better image resolution and faster image capture time.
Data Processing Requirements	No additional data processing required.	Requires additional data processing in the FPGA (FWOCT).

FWOCT	Mode 1	Mode 2	Mode 3
Re-mapping using k-clock rising edge	x
Re-mapping using k-clock rising & falling edge		x
Re-mapping using K-clock interpolation			x
K-clock Frequency Range FS = Digitizer Sampling Rate (e.g ADQ32 = 2.5GHz)	4MHz to 40% of FS ADQ32 (up to 1GHz) ADQ35 (up to 2GHz)	4MHz to 40% of FS ADQ32 (up to 1GHz) ADQ35 (up to 2GHz)	4MHz to 40% of FS ADQ32 (up to 1GHz) ADQ35 (up to 2GHz)
OCT Frequency Range	0Hz to K-clock freq/2 (0Hz to 1GHz: ADQ35)	0Hz to K-clock freq (0Hz to 2GHz: ADQ35)	0Hz to K-clock freq (0Hz to 2GHz: ADQ35)
FFT	x ADQ32/33 (8k) ADQ35 (32k)	x ADQ32/33 (8k) ADQ35 (32k	x ADQ32/33 (8k) ADQ35 (32k)
Background Correction (BC)	x	x	x
Windowing & Dispersion Compensation (W & DC)	x	x	x

Mode 1 - Maps the rising edge of the k-clock (zero-crossing points)

Supports max k-clock up to 80% of Nyquist (40% of sampling rate)
Supports OCT signal frequency up to 50% of k-clock frequency

E.g., ADQ32. At FS = 2.5 GSPS, k-clock max = 1 GHz & OCT signal max = 500 MHz.

Mode 2 - Maps both the rising and falling edges of the k-clock

Enables system to half the frequency of the K-clock or double the OCT signal frequency.

Supports max k-clock up to 80% of Nyquist (40% of sampling rate)
Supports OCT signal frequency up to 100% of k-clock frequency

E.g., ADQ32 At FS = 2.5 GSPS, k-clock max = 1 GHz & OCT signal max = 1 GHz

With version 1, SS-OCT max = 500 MHz for 1 GHz K-clock.

E.g., 2 ADQ35/36 use case. At FS = 5 GSPS, k-clock max = 2 GHz & OCT signal max = 2 GHz
Doubles the bandwidth of the OCT signal which is sampled by the rising and falling edges of the k-clock.

Mode 3 – Supports higher interpolation to extract sample points at sub harmonic instants (e.g. 0, π/2, π, 3π/2, 2π)

Software programmable.
Enables lower frequency k-clock/MZI clock frequencies
All modes – FWOCT includes Background Correction, Windowing & Dispersion Compensation, FFT (8k, 32k). Description on following slide.
See the FWOCT users guide section for more details

Feature	Implementation	Comment
Background correction Subtraction of a unique value for each sample point.	16-bit values The number of values is the same as the number of FFT points.	A known background pattern can be removed from the collected signal before the FFT. This is done by writing a unique real-valued constant for each input index.
Windowing & Dispersion Compensation Multiplication with a unique complex value for each sample point	The real and imaginary part of each value are 16 bits each (2 integer bits and 14 fractional bits). The number of values is the same as the number of FFT points.	The collected signal can be windowed and dispersion-compensated before the FFT. This is done by writing a unique complex-value constant for each input index.
FFT	8k points (ADQ32, 33). 32K points (ADQ35)	An FFT core exists on the FPGA.
Magnitude function Takes the FFT output and provides The squared absolute value or the logarithmic value.	3 Output Modes Exist: Passthrough Squared absolute: Re(x)^2 + Im(x)^2 10*log10(squared absolute)	Passthrough: The output remains unchanged and is simply the complex-valued FFT output x. Squared Magnitude: The output is jxj2. Logarithmic Scale: The output is 10 log10(jxj2).

Product	Comment
ADQ32	Order code ADQ32-FWOCT
ADQ33	Order code ADQ33-FWOCT
ADQ35	Order code ADQ33-FWOCT
ADQ36	Order code ADQ36-FWOCT

Swept-Source Optical Coherence Tomography (SS-OCT)